# FPGA subtree only. src/fpga is not part of the hashcat build. Almost everything below is regenerated
# by Vivado, LiteX or make, so it is kept out of git. Patterns have no leading slash, so they apply at
# any depth under src/fpga, which means every board and target subfolder.

# Vivado + LiteX build tree (regenerated by the SoC build script)
build/
dist/

# The LitePCIe kernel module lives in ONE place, driver/, for every algorithm. Its source is tracked so
# the driver builds from a clean checkout against a downloaded bitstream, without Vivado. Only what
# kbuild produces is ignored. csr.h and soc.h are generated by the SoC build but tracked on purpose:
# main.c includes both, there is no prebuilt module to ship because it has to match the user's kernel,
# and a user who downloads a bitstream never runs Vivado.
driver/*.ko
driver/*.mod
driver/*.mod.c
driver/*.o
driver/.*.cmd
driver/modules.order
driver/Module.symvers
driver/.tmp_versions/

# Each LiteX board build writes its generated csr.h, soc.h and mem.h to <algo>/software/kernel/<board>/.
# They are build output and stay out of git. 'make -C src/fpga headers' checks that every board's copy
# agrees and copies the shared map into driver/, and that copy is tracked.
**/software/kernel/*/

# Compiled host tooling, regenerated by make. Deny by default and re-admit sources, rather than listing
# binary names: a name list silently misses every tool added later, which is how a compiled binary ended
# up staged once already.
*.o
*.d
*.a
**/software/user/*
!**/software/user/*.c
!**/software/user/*.h
!**/software/user/*.py
!**/software/user/Makefile
!**/software/user/liblitepcie/
!**/software/user/liblitepcie/*.c
!**/software/user/liblitepcie/*.h

# Python bytecode
__pycache__/
*.pyc

# simulation scratch (iverilog / Vivado xsim)
*.vvp
*.vcd
xsim.dir/
*.jou
*.pb
*.wdb
.Xil/

# The simulation scripts write under build/ by default, which the build/ rule covers. These cover a
# SIM_WORK pointed at a work directory inside the tree.
work/
work[0-9]*/
work_*/
