What about R9 Nano? Benchmarks?

[epixoip]

Not necessarily. Floating point operations are handled by the FPUs, not the ALUs. Each CUDA core currently has one FPU and one ALU (referred to in the diagram below as the "FP unit and "INT unit.")



So, they could double the FLOPS by simply doubling the FPU count, e.g. each CUDA core could have two FP units and one INT unit, and the scheduler could dispatch four FP32 operations per clock cycle instead of two.

Also with the die shrink, increasing the clock rate is indeed a possibility. 

We won't really know more until actual details are released. Until then this is all just rumors and speculation. Go buy a Maxwell card already