Cosmetic Bug?
#1
The speed display is outputted under Dev1, when Dev2 is the device working.

Status.........: Running
Hash.Type......: scrypt
Speed.Dev.#1...:  1798.4 kH/s (0.00ms)
Speed.Dev.#2...:        0 H/s (33494.79ms)
Speed.Dev.#3...:        0 H/s (0.00ms)
Speed.Dev.#4...:        0 H/s (0.00ms)
Speed.Dev.#*...:  1798.4 kH/s
Recovered......: 0/771423 (0.00%) Digests, 0/771423 (0.00%) Salts
Recovered/Time.: CUR:0,N/A,N/A AVG:0.00,0.00,0.00 (Min,Hour,Day)
Progress.......: 210950/792251421 (0.03%)
Rejected.......: 0/210950 (0.00%)
Restore.Point..: 0/1027 (0.00%)
HWMon.Dev.#1...: Temp: 37c Fan: 26% Util:  0% Core: 135Mhz Mem: 324Mhz Lanes:16
HWMon.Dev.#2...: Temp: 53c Fan: 32% Util: 99% Core:1265Mhz Mem:3004Mhz Lanes:16
HWMon.Dev.#3...: Temp: 34c Fan: 26% Util:  0% Core: 135Mhz Mem: 324Mhz Lanes:16
HWMon.Dev.#4...: Temp: 34c Fan: 26% Util:  0% Core: 135Mhz Mem: 324Mhz Lanes:16

Topology
GPU0 GPU1 GPU2 GPU3 CPU Affinity
GPU0 X        PIX     PHB   PHB    0-19
GPU1 PIX     X        PHB   PHB    0-19
GPU2 PHB   PHB    X        PIX     0-19
GPU3 PHB   PHB    PIX     X        0-19

Legend:

 X   = Self
 SOC = Path traverses a socket-level link (e.g. QPI)
 PHB = Path traverses a PCIe host bridge
 PXB = Path traverses multiple PCIe internal switches
 PIX = Path traverses a PCIe internal switch
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#2
It depends largely on xorg.conf. Hashcat doesn't do any reordering, it takes it 1:1 as it comes from the runtime.
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